Dhiraj K Pradhan

Dhiraj K Pradhan

Professor of Computer Science, University of Bristol
Verified email at cs.bris.ac.uk
Cited by 15353
Fault tolerance Logic Synthesis Computer architecture error correcting codes Galois Field
Marek Perkowski

Marek Perkowski

Professor of Electrical and Computer Engineering, Portland State University
Verified email at pdx.edu
Cited by 9674
multiple-valued logic reversible logic logic synthesis quantum computing
Niklas Een

Niklas Een

Researcher at RenTec
Verified email at een.se
Cited by 9599
Machine Learning Formal verification Logic synthesis
Tsutomu Sasao

Tsutomu Sasao

Visiting Professor, Meiji University
Verified email at cs.meiji.ac.jp
Cited by 9235
Logic synthesis Multiple-valued logic Logic Design Switching Theory
Alexander Barkalov

Alexander Barkalov

Professor, University of Zielona Góra
Verified email at iie.uz.zgora.pl
Cited by 6822
Logic Synthesis Control Units VLSI
Mathias Soeken

Mathias Soeken

Microsoft
Verified email at epfl.ch
Cited by 5819
Computer Science Logic Synthesis Quantum Computing
Gerhard W Dueck

Gerhard W Dueck

Professor of Computer Science, University of New Brunswick
Verified email at unb.ca
Cited by 5474
Logic Synthesis Reversible Logic Garbage Collection
Marc Riedel

Marc Riedel

Full Professor of Electrical and Computer Engineering, University of Minnesota
Verified email at umn.edu
Cited by 5098
Logic Synthesis Logic Verification Formal Verification Synthetic Biology Molecular Computing
Fabrizio Ferrandi

Fabrizio Ferrandi

Politecnico di Milano
Verified email at polimi.it
Cited by 4213
High-Level Synthesis HW/SW codesign Reconfigurable Computing Logic synthesis Embedded Systems
Md. Mazder Rahman

Md. Mazder Rahman

University of New Brunswick, Canada
Verified email at unb.ca
Cited by 3783
Logic Synthesis Reversible Logic Synthesis and Optimization Quantum Circuits
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